1. Field of the Invention
The present invention relates to a data driven information processor, and more particularly, to a data driven information processor having a data driven type information processing unit and a memory to be accessed upon execution of information processing by the processing unit, and capable of improving efficiency of access to the memory.
2. Description of the Background Art
A data driven information processor is one type of non-von-Neumann computer having no concept of sequential execution of instructions by a program counter. Such a data driven information processor employs architecture based on parallel processing of instructions. In the data driven information processor, an execution of an instruction is enabled upon a collection of data to be operated, and a plurality of instructions are simultaneously driven by data, so that programs are executed in parallel in accordance with a natural flow of the data. As a result, time required for operation will be drastically reduced compared to the case of von-Neumann computers. In order to further improve a processing speed of the data driven information processor, the speeding up of access to a memory (hereinafter referred to as a data memory) for storing data to be referred to or updated upon execution of processing is desired.
FIG. 13 is a diagram showing the connection of a conventional data driven processor and an external data memory, and FIG. 14 is a diagram showing connection of a plurality of conventional data driven processors and external data memories.
FIG. 15 is a diagram showing a structure of a memory interface for a conventional data driven processor.
In conventional data driven processors, a multi-processor system consisting of a plurality of processors and a plurality of memory interfaces is proposed in an article entitled "An Evaluation of Parallel-Processing in the Dynamic Data Driven Processor", pp. 9-18 issued on Nov. 12, 1991 in the Micro Computer Architecture Symposium sponsored by Information Processing Society of Japan.
In the conventional processor proposed therein, although a data memory (hereinafter referred to as an internal data memory) incorporated into the processor or a data memory (hereinafter referred to as an external data memory) located external to the processor is connected to a single memory interface, data cannot be read/written from and to both memories simultaneously. In other words, since the conventional data driven processor allows an access to only one data memory for one memory interface, only one data can be accessed for a single access time (see FIG. 13). Accordingly, a double access time is required to access data in both internal and external data memories, so that the speeding up of processing has been prevented.
In addition, in the conventional data driven processor, although an addresses of a data memory is modified by address modification, addresses in a plurality of different data memories cannot be modified using this address modification. Therefore, in order to access first and second data memories, first and second memory interfaces for respectively accessing to the first and the second memories are required as shown in FIG. 14, thereby causing an increase in cost and preventing a reduction in device size.
Furthermore, in the conventional data driven information processor, an internal data memory and a cache memory are not provided separately, and therefore, there has been no facility which accesses data in each of the internal data memory and the cache memory simultaneously.
In addition, the conventional data driven processor is not provided with a function to store a program in a memory interface, and therefore, a data memory cannot be accessed without processing by a host processor (see FIG. 15). Accordingly, frequent accesses to the data memory cause an increase in load on the host processor, so that speeding up of the whole processing has been prevented.